In this post I am going to look at test bench data files. As circuits become more complex there will be more test cases for inputs. It will become increasingly tedious to write code for each of the possible test cases for inputs. So I want to see if I can simply testing before then. […]
Test Bench Data Files in Verilog Read More »
For this post I thought it might be interesting to take a look at Verilog user-defined primitives (UDPs). Recall that some time ago I built an Exclusive Or circuit (XOR) using the built-in Verilog operator. I’ll build the same circuit using Verilog user-defined primitives. A Verilog UDP allows you to specify a circuit by defining
A Look At Verilog User-Defined Primitives Read More »
Lets revisit the seven-segment display and this time use all four digits. To do that I will use a multiplexer circuit (MUX). The MUX will cycle through the display of the digits one at a time. The term multiplexer is just a fancy way of saying data selector. A multiplexer circuit simply selects a single
Multiplexer Circuit for the Seven-Segment Display Read More »
For this next project I am going to take some time to learn and explore another peripheral. Specifically the Pmod Keypad. If you are a reader of this blog you may remember that earlier I discussed the Basys 3 Pmod pack. The Pmod pack includes a total of five peripherals to explore. I purchased the
Pmod Keypad Peripheral First Look Read More »
In earlier posts I discussed the Verilog plugin and syntax highlighting. And at that time I mentioned that I also created a plugin for constraint files. I am happy to share that the plugin for Xilinx Design Constraint (XDC) files is also now available on WordPress.org. I will try to keep this plugin up to
Xilinx Design Constraint WordPress Plugin is Now Available Read More »
For this project I am going back to exploring new peripherals. In this case the seven-segment display on the Basys 3 board. To keep things simple I am only going to work on displaying digits, specifically hexadecimal digits, on just one of the four digits of the seven-segment display. In a future project I’ll tackle
Seven-Segment Display – An Initial Exploration Read More »
I’ve been pretty active in launching this site. The early topics quite honestly take more time to write up than to develop. And I have quite a list of ideas for the introductory topics. This is just a quick note to share that FPGA Coding was recently added to the list of the Top 15 Field-programmable
Starting to Get Noticed Read More »
If you are following the syntax highlighting topic you will know that I was not able to find a good syntax highlighter plugin for WordPress that supported Verilog. So I recently created my own and submitted it to WordPress.org. There was some back and forth with the reviewers around naming and trademark policies. But that
Verilog WordPress Plugin Is Now Available Read More »
I am going to build an LED counter circuit. The LED counter uses the configurable counter circuit and the configurable shift register created earlier. Using those two components I will build a circuit that cycles through the LEDs. Recall from the configurable shift register post that we needed a way to slow down the shift
LED Counter Circuit Using A Shift Register Read More »
I expect to share many more Xilinx constraint files in the future. And that being the case, it seems to make sense to take the time to create a plugin for Xilinx Constraint files (XDC). Given what I learned through creation of the Verilog syntax highlighting WordPress plugin I have a strong foundation to build
Xilinx Constraint Files And The Syntax Highlighter Read More »
