It is back to FPGA topics for this next article. This time we are going to be exploring register files. A register file is nothing more than an array, collection or “file” of registers. We have encountered registers before, first when I introduced sequential circuits and the Verilog reg keyword. A register is nothing more […]
Exploring Register Files Read More »
In this post I am going to look at test bench data files. As circuits become more complex there will be more test cases for inputs. It will become increasingly tedious to write code for each of the possible test cases for inputs. So I want to see if I can simply testing before then.
Test Bench Data Files in Verilog Read More »
I am going to build an LED counter circuit. The LED counter uses the configurable counter circuit and the configurable shift register created earlier. Using those two components I will build a circuit that cycles through the LEDs. Recall from the configurable shift register post that we needed a way to slow down the shift
LED Counter Circuit Using A Shift Register Read More »
I will confess that I’ve been withholding some important information from you. I’ve touched upon the subject in several previous posts like the Verilog Introduction, or D-type Flip Flop. And if you’ve been trying to follow along using the source code from github you’ve surely caught me. I am surprised that no one has commented
Test Bench for Verilog Behavioral Simulation Read More »
