Verilog or VHDL Which Is The Best Choice?

The question of which Hardware Definition Language (HDL) to use, Verilog or VHDL, is one of the first things you will encounter once you get ready to start coding for your FPGA device. After choosing my hardware, I confronted this question myself and started research the options. You can find many opinions online, but one that I like is this article on the Digilent blog. If you are trying to answer this question for yourself, I encourage you to read the full article.

In Verilog, the language is more compact, as the Verilog language is more of a hardware modeling language. You will end up typing few lines of code and it draws similarities to the C language. 

The short version is that Verilog has a C-like syntax. If you are a C programmer you will find that Verilog code looks pretty familiar. Verilog code, like C code, tends to be more compact. Verilog focuses a bit more on correctly modeling lower-level hardware features.

One of the key features of VHDL is that it is a strongly typed language, which means that each data type (integer, character, or etc.) has been predefined by the language itself. All values or variables defined in this language must be described by one of the data types.

VHDL on the other-hand has stronger type safety requirements than Verilog. It trades some extra verbosity, often in the form of required type declarations, for added clarity and type safety. In that sense you could say that VHDL has a Pascal-like or maybe even Ada-like syntax. The choice to prioritize syntax and type-safety is not surprising given that the Department of Defense created VHDL in the 1980’s at roughly about the same time as Ada. Both Pascal and Ada prioritize strong type-safety. If you plan to work for a defense contractor, then you should probably choose VHDL.

How do they compare?

Below are two examples of a basic D-flipflop in Verilog and VHDL respectively. I’ve left out some of the setup code for clarity. And don’t worry about making sense of the code. We’ll talk about what the code does later. For now just take note of the syntax differences.

reg q;
always @(posedge clk or posedge reset)
  if(reset)
    q <= 0;
  else
    q <= d;

DFF : process(all) is
begin
  if RST then
    Q <= '0';
  elsif rising_edge(CLK) then
    Q <= D;
  end if;
end process DFF;

My choice?

Though at times I work in many different programming languages including Javascript, C#, Swift and Java, and I’ve certainly written plenty of Pascal code (mainly Turbo Pascal and Delphi). But my primary programming language is C/C++. What my most frequently used programming languages all have in common is a core syntax that traces its roots back to the original C programming language.

And so for me the choice to use Verilog over VHDL was pretty easy. Once I fully explore Verilog maybe it will be time to look more closely at VHDL. Perhaps in a future post I’ll offer some comparisons between actual designs in Verilog vs. VDHL.