For the next project I am going to create a D-type flip flop (D-FF). This is a very simple sequential circuit. If you don’t recall what that is you may want to read this earlier post. There are many different kinds of flip flops, they are a common building block of digital circuits. Flip flops are sequential circuits, meaning they have memory. A flip flop holds 1-bit of memory, while a collection of eight D-FF’s can form an 8-bit data register.
The D-FF is quite simple. As a sequential circuit, it of course requires a clk port. It commonly also has an input d and an output q. At the rising, or positive, edge of the clk signal the D-FF samples d and sets that as its output q. The D-FF remembers and continues to present the last value of q until a new value is set. Recall that we use the reg type when we want a signal to retain its previous value until it is changed.
This implies that our output q must be of type reg. To implement that behavior we need only declare output q to be of type reg instead of wire in our module declaration. Then, we use an always block, sensitive to the positive edge of clk to sample d and assign it to q. Remember that we use a non-blocking assignment (operator <=) inside an always block for sequential circuits. Put it all together and you have the code below.
module dff(
input clk,
input d,
output reg q
);
// each clock sample d and output as q
always @(posedge clk)
q <= d;
endmodule
And the results?
That is not a lot of Verilog, but does it work as expected? Run a Behavioral Simulation in Vivado and look at the waveform and you will see something like the following.
Note how the change at output q changes only on the rising edge of clk signal? This happens even though the input d changes earlier. This delay is the D in D-FF. Although given the common use of the D-FF to form data registers, some people counter that the D in D-FF should stand for data. The change in output is synchronized to the clock signal even if the input changes just after the rising edge of the last clock.
That’s all for now. The source code for this project is on the github site. Please leave a comment if you have any feedback, questions or suggestions!