One thing that you come across when you start working with the Xilinx Vivado tools for FPGA development is the concept of constraint files. Every project you create will need a constraint file in addition to one or more Verilog source files. Digilent conveniently provides a set of Xilinx design constraint files for all of the boards that they support. You acquire these files when you download the board files from Digilent’s github site.
Xilinx constraint files end in .XDC. Perhaps not surprisingly, XDC stands for Xilinx Design Constraints.
When you create your project in Vivado, one of the first things you will add a copy of the Basys 3 design constraint file provided by Digilent. Why do we add a copy? Because as part of your project you will make changes to the constraints file. And you do not want those changes to be made to your master copy of the file. I’ve shown the Vivado Add Sources dialog below. When adding constraint files, you will select Add or create constraints.
But what exactly is a constraint file and why do we need one? A constraint file tells Vivado how to connect the IO pins on the Artix-7 to user-friendly names that you reference in your Verilog files. I’ve provided a small sample of the design constraint file for the Basys 3 below. In this example you can see a few lines after ## Clock signal that are commented out. Constraint files use the ‘#’ character at the start of a line to define a comment. The Basys 3 constraint file provided by Digilent has commented out definitions for all of the peripheral IO connections available.
## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
#set_property PACKAGE_PIN W5 [get_ports clk]
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
In order to map the Verilog signal named clk to the actual hardware clock we must uncomment out the 3 lines following ## Clock signal by removing the ‘#’ character. After we do so the start of the file should look like the image below. I’ve also added the constraints for one of the on-board LED’s to the file. While I was at it, I also renamed the LED I was using from led[0] to simply led. Which emphasizes the fact that you have the ability to change the name of the IO ports. You can, and should change the name to whatever will make sense to you in your Verilog code.
## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {led}]
set_property IOSTANDARD LVCMOS33 [get_ports {led}]
So now we have both a clk signal as well as an led signal. We saw the clk signal in an earlier post but I did not explain the origin of that input signal. Now we know where the signal definition comes from – the constraint file! We will use the clk and led signals in an upcoming project. The Basys 3 constraint file provided by Digilent conveniently provides commented out definitions for all of the peripheral connects available.
That’s all for now. If you have a question or feedback about something in this post, please leave a comment!