Building An Exclusive Or Circuit

Ok, now the development environment is setup. And we have solved my Hyper-V issue. For our first official Verilog design let’s tackle something simple that builds upon what we’ve already covered in earlier posts. Let’s build an Exclusive Or circuit (XOR), which is a simple two-input, one-output logic gate. Exclusive Or circuits are one of the basic building blocks of digital logic along with AND, OR and NOT.

These types of basic circuits are called Combinational Circuits or Combinational Logic. This sounds complex at first, but in fact all that combinational logic means is that the output is purely a function of the inputs at any point in time. There is no memory, or state, in a combinational circuit. Circuits that have memory are called Sequential Circuits. We will talk more about sequential circuits another time.

If you are unfamiliar with how XOR works it is pretty simple. It is defined to return true (1) at the output if either of the inputs, but not both, are true (1). You can see this behavior expressed in the form of a truth table below.

Exclusive Or Circuit in Verilog

How would we implement this in Verilog? First, we need to define our input and output ports. We already know how to do this from our brief introduction to Verilog. So in our module declaration we declare a and b as input wire ports. And we declare d as an output wire. How do we implement an XOR? Verilog conveniently provides a built-in operator (^) which instructs Verilog to generate an XOR gate. Next we simply connect the output of a ^ b to our output d via a continuous assignment. The complete code for our XOR circuit is shown below.

There are other ways to do this in Verilog, for example, using user defined primitives (UDP). Verilog UDP’s allow you to provide a truth table to describe behavior. Verilog also provides primitives for the basic logic gates. I may explore built-in Verilog primitives and UDP’s another time. For now we will use the Verilog operator method.

module xor_gate(
    input wire a,
    input wire b,
    output wire d
    );
    
    // perform exclusive-or of a and b and assign result to d
    assign d = a ^ b;
endmodule

But does the circuit work?

To check, lets run a Behavioral Simulation in Vivado with a range of inputs. Doing so generates the waveform shown below. In the image we can see that at 20ns, when a and b are 0, d is 0. Later at 40ns, when a is 1 and b is 0, d is 1. And so on with results at 60 and 80ns. Comparing the results of the simulation with the truth table confirms that we have designed a circuit which correctly implements an Exclusive Or circuit.

That’s it for now! We have successfully designed and tested a simple combinational circuit that does a little more than pass the input to the output. You can find the source code for this project on GitHub here.

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