Verilog Keywords

While I am learning I often find it useful to keep an up-to-date list of common Verilog and SystemVerilog keywords handy. I built this page as a simple cheat sheet for myself, and I will keep adding to it as I progress. Note that I have not attempted to provide a complete reference of the IEEE-1364 Verilog standard. I am including primarily those keywords that I find are most commonly used. In particular I focus on those keywords most useful for synthesis and for testbench creation.

always	always_comb	always_ff
always_latch	assign	begin
case	else	end
endcase	endfunction	endmodule
endprimitive	endtable	endtask
enum	for	forever
function	if	initial
input	int	localparam
logic	module	negedge
output	parameter	posedge
primitive	real	reg
repeat	table	task
time	timescale	typedef
while	wire

Note also that I haven’t differentiated between the various Verilog standards: Verilog-95, Verilog-2001 or Verilog-2005. Nor have I differentiated between Verilog and SystemVerilog. If that seems important drop me a comment and let me know and I can add a legend or split the table out by standard or major dialect. You can read more about Verilog here. See also the list of Verilog operators.

Most important Verilog keywords

1. module: A building block in Verilog that defines a hardware module. It is always terminated with **endmodule**. The module keyword is followed by the circuit name and a port list, where each port can be either an input or an output.
2. assign: Creates combinational logic. It assigns a value to a wire or register.
3. case: Defines conditional branching based on the value of an expression.
4. while: Defines loop constructs.
5. wire and reg: These are data types in Verilog. wire represents a continuous assignment, while reg represents a register.
6. Logical operators: Keywords like and, or, and nand are used for logical operations.
7. System tasks and functions: Verilog includes built-in system tasks and functions that perform specific actions, such as $display, $monitor, and $finish.